This application claims the benefit of a Japanese Patent Application No. 2002-074731 filed Mar. 18, 2002 in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device used as a ferroelectric memory.
2. Description of the Related Art
Ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) is known as a nonvolatile memory capable of storing information even when the power is turned OFF. Many conventional ferroelectric memories have a planar-type structure formed on an insulating film covering the memory cell transistor. Ferroelectric memory is characterized in that it is a voltage driven element, has low power consumption, and operates at a very high speed compared to flash memory or EEPROM.
Moreover, the ferroelectric memory presented in an academic conference has a COB (Capacitor Over Bit line) structure used in a DRAM (Dynamic Random Access Memory). This COB structure is a structure in which the ferroelectric capacitor is formed above the bit line pattern after the bit line pattern is formed. In the COB structure, since the bit line pattern is formed before the memory cell capacitor is formed, the bit line pattern can be formed on a flat plane; and this structure can be widely used in DRAMs where it is necessary to increase the surface area using a memory cell capacitor of complex shape.
In the FeRAM market, many applications for system LSI such as smart card and the like can be found. Therefore, using the CMOS process as the forming step, there is a need to decrease the size for additional memory cells and achieve high integration density.
Furthermore, although the COB structure is, as mentioned above, a suitable structure for DRAM in that the bit line pattern can be formed on a flat plane even if the size of the ferroelectric capacitor is increased, the bit lines are formed before the ferroelectric capacitor in a manufacturing step. Thus, when the COB structure is used for FeRAM, there is a need to prevent oxidation or melting of bit line patterns during heat treatment in an oxidation atmosphere for crystallization or for oxygen loss compensation of the ferroelectric film. For example, Al pattern melts when the processing temperature exceeds 500xc2x0 C. In a polycrystalline silicon pattern, oxidation may occur due to heat treatment in an oxidation atmosphere.
Accordingly, it is a general object of the present invention to provide a semiconductor device that achieves high integration density and is easy to manufacture.
The present invention achieves the above object by providing a semiconductor device having a substrate; a plurality of memory cell transistors formed on the substrate and arranged in arrays in a first direction and in a second direction different from the first direction, each of the memory cell transistor being provided with a first and a second diffusion legion; a ferroelectric capacitor connected to the first diffusion region in each of the plurality of memory cell transistors via a first contact plug; a plurality of bit lines formed above the ferroelectric capacitor, and connected to the second diffusion regions of the memory cell transistors arranged in the first direction via a second contact plug, each bit line being extended in the first direction and arranged next to each other in the second direction; a plurality of word lines formed between the first and second contact plugs of each memory cell transistors, each word line being extended in the second direction and arranged next to each other in the first direction; and a plurality of plate lines each being extended in the second direction and arranged next to each other in the first direction, the plate lines being connected to upper electrodes of a group of the ferroelectric capacitors arranged in the second direction through a plurality of contact holes; wherein each of the word lines is bent away from an opposing other word line in areas near the second contact plugs, and toward the other word line in other areas; and the plurality of contact holes is displaced alternately with respect to a longitudinal centerline of the plate line.
In this way, by forming the word line so that it is bent away from the opposing other word line in areas near the second contact plug, and toward the other word line in other areas, and by forming the contact hole for connecting the plate line and the upper electrode of the ferroelectric capacitor, displaced alternately with respect to the longitudinal center line of the plate line, the size of the memory cell is reduced and higher integration density can be achieved compared to forming the word line linearly and bending it away from the other word lines even in areas not near the second contact plugs and forming the contact hole on the centerline of the plate line.
Furthermore, compared to DRAM, in FeRAM, there is no need to increase the size or the surface area of the ferroelectric capacitor and its capacitance, and thus the ferroelectric capacitor is relatively simple and has a low height structure. Here, even if CUB (Capacitor Under Bit Line) structure for forming the bit line above the ferroelectric capacitor in FeRAM is used, the formation of the bit line will not be complicated. Moreover, because the bit line is formed after the ferroelectric capacitance, the bit line will not oxidize or melt during heat treatment for suppressing oxygen loss of the ferroelectric film. Therefore, manufacturing is facilitated.
The present invention further achieves the above object by providing a semiconductor device having a substrate; a plurality of memory cell transistors formed on the substrate and forming arrays; a ferroelectric capacitor connected to a first diffusion region of the memory cell transistor in each of the memory cell transistors; and a plurality of bit lines formed above the ferroelectric capacitor, and each bit line being connected commonly to a second diffusion region of a group of the memory cell transistors.
The present invention further achieves the above object by providing a semiconductor device having a substrate; a memory cell transistor formed on the substrate and provided with a first and a second diffusion region; a ferroelectric capacitor connected to the first diffusion region in the memory cell transistor via a first contact plug; a bit line formed above the ferroelectric capacitor, and connected to the second diffusion region via a second contact plug; a word line formed between the first and the second contact plug; and a plurality of plate lines connected to upper electrodes of the ferroelectric capacitors through contact holes; wherein the plate line comprises projecting portions on one side of its extending direction; and the contact hole being formed on the projecting portions.
The present invention further achieves the above object by providing a semiconductor device having a substrate; a memory cell transistor array formed on the substrate; a ferroelectric capacitor provided in each of the memory cell transistors; a word line being extended as a gate electrode in a group of the memory cell transistor arranged in a first direction; a plate line being extended in the first direction and connected to the group of the memory cell transistors arranged in the first direction through each of a plurality of contact holes; and a bit line being extended in a second direction and connected to a group of the ferroelectric capacitors arranged in the second direction via each of a plurality of contact plugs; wherein the word line is bent with respect to the first direction so as to move away from an opposing other word line in areas near the contact plug, and move toward the other word line in other areas; the plate line having a plurality of projecting portions displaced alternately with respect to the first direction; the projecting portion projecting in a bent direction of the word line; each of the contact hole being formed on the projecting portion.
The present invention further achieves the above object by providing a method of manufacturing a semiconductor device having the steps of forming a memory cell transistor on a substrate; performing heat treatment on a ferroelectric film of a ferroelectric capacitor; forming a contact plug connected to the memory cell transistor after the step of performing heat treatment; forming a bit line connected to the memory cell transistor via the contact plug somewhere above the ferroelectric capacitor; forming a word line adjacent to the contact plug so as to be bent away from an opposing other word line in areas near the contact plug, and toward the other word line in other areas; forming a plate line; and forming a contact hole for connecting an upper electrode of the ferroelectric capacitor and the plate line at a position deviating from a longitudinal centerline of the plate line.